I2C Protocol, bus and Interface: A Brief Introduction ~ CasinoDigitalTech

Introduction of I2C Protocol

An I2C protocol is one of the serial communication protocol that is used for the chip to chip communication. Similar to the I2C protocol, SPI and UART also used for the chip to chip communication.

The I2C is the short form of Inter-Integrated Circuit, is a type of bus, which designed and developed by Philips in 1980 for inter-chip communication.I2C is adopted by a lot of vendor companies for the chip to chip communication.

It is a multi-master and multi-slave serial communication protocol means that we have the freedom to attach multiple IC at a time with the same bus. In I2C protocol, communication always started by the master and in the case of multi-master, only one master has the ownership of the bus.

In this article, you will learn the I2C protocol and its bus configuration and uses in the chip to chip communication.

What is I2C?

I2C is a serial communication protocol. It provides the good support to the slow devices, for example, EEPROM, ADC, and RTC etc. I2c is not only used with the single board but also used with the other external components which have connected with boards through the cables.

I2C is basically two-wire communication protocol. It uses only two wire for the communication. In which one wire is used for the data (SDA) and other wire is used for the clock (SCL).

In I2C, both buses are bidirectional, which means master able to send and receive the data from the slave. The clock bus is controlled by the master but in some situations slave is also able to suppress the clock signal, but we will discuss it later.

Additionally, an I2C bus is used in the various control architecture, for example, SMBus (System Management Bus), PMBus (Power Management Bus), IPMI (Intelligent Platform Management Interface) etc.

Why use I2C

Unlike the serial com port I2c is the synchronous communication, in I2C both master and slave use the shared clock which is produced by the master.

In serial port, both the transmitter and receiver device have own clock generator. Hence it is very important to minimize the difference between the clock of the transmitter and slave otherwise data will be corrupt during the communication.

Another disadvantage of asynchronous serial com port is that only two devices transmit and receive the data but beside it, I2C can be multi-master and multi-slave.

Asynchronous serial is used a UART chip for the communication.
There is no specific limit defined for the asynchronous communication but most of the serial devices support up to the maximum baud rate 230400 (bits per second).

SPI is full duplex and faster than I2c Although sometimes I2C is much easier and beneficial. In I2C, we needed only two wire for the communication but in SPI we have needed four wire for the communication.I2c can be multi-master but SPI never can be multi-master.

These are some advantage which forced to us to use the I2C protocol in communication.

Feature of I2C Bus

In I2C only two buses are required for the communication, the serial data bus (SDA) and serial clock bus (SCL).
Each component in I2C bus is software addressable by a unique address, this unique address is used by the master to communicate with a particular slave.
Always a master and slave relationships exist at all times in I2C.
In I2C, Always communication is started by the master.
The I2C bus provides the ability of the arbitration and collision detection.
I2C is the 8-bit oriented serial bidirectional communication, there are following speed mode in I2C

MODE	SPEED
Standard-mode	100 kbit/s
Fast-mode	400 kbit/s
Fast-mode Plus	1 Mbit/s
High-speed mode	3.4 Mbit/s

I2C Physical layer

I2C is pure master and slave communication protocol, it can be the multi-master or multi-slave but we generally see a single master in I2C communication. In I2C only two wire are used for communication, one is data bus (SDA) and the second one is the clock bus (CLK).

All slave and master are connected with same data and clock bus, here important thing is to remember these buses are connected to each other using the WIRE-AND configuration which is done by to putting both pins is open drain. The wire-AND configuration allows in I2C to connect multiple nodes to the bus without any short circuits from signal contention.

The open drain allows the master and slave to drive the line low and release to high impedance state. So In that situation, when master and slave release the bus, need a pull resistor to pull the line high. The value of the pull-up resistor is very important as per the perspective of the design of I2C system because the incorrect value of pull-up resistor can lead to signal loss.

Note: We know that I2c communication protocol supports the multiple masters and multiple slaves, but most system designs include only one master.

I2C protocol

I2C is the very easy chip to chip communication protocol. In I2C, communication is always started by the master. When the master wants to communicate with slave then he asserts a start bit followed by the slave address with read/write bit.
After the asserting of the start bit, all slave comes in the attentive mode. If the transmitted address match with any of the slave on the bus then an ACKNOWLEDGEMENT (ACK) bit is sent by the slave to the master.

After getting the ACK bit master start the communication. If there is no slave whose address match with the transmitted address then master received a NOT-ACKNOWLEDGEMENT (NACK) bit, in that situation either master assert the stop bit to stop the communication or assert a repeated start bit on the line for new communication.

Data Frame overview of I2C protocol

I2C is an eight-bit communication protocol, in I2C we get ACK (acknowledgment) or NACK (Not Acknowledgment) bits after each byte. Here, I am describing some important terms which related to I2c data frame.

START CONDITION

The default state of SDA and SCL line is high. A master asserts the start condition on the line to start the communication. A high to low transition of SDA line while the SCL line is high called the START condition. The START condition is always asserted by the master. The I2C bus is considered busy after the assertion of the START bit.

STOP CONDITION

The STOP condition is asserted by the master to stop the communication. A Low to high transition of SDA line while the SCL line is high called the STOP condition. The STOP condition is always asserted by the master. The I2C bus is considered free after the assertion of the STOP bit.

Note: A START and STOP condition always asserted by the master.

REPEATED START

The repeated start condition similar to the START condition but both are different to each other. The repeated start is asserted by the master before the stop condition (When the bus is not in an idle state).

A Repeated Start condition is asserted by the master when he does not want to lose their control from the bus. The repeated start is beneficial for the master when it wants to start a new communication without the asserting the stop condition.

Note: Repeated start is beneficial when more than one master connected with the I2c Bus.

BYTE FORMAT IN I2C PROTOCOL

In I2C, every data which is transmitted over the SDA line must be eight-bit longs. It is very important to remember in I2c that data bit is always transmitted from the MSB and we can send or receive any number of bytes in I2C between the start and stop condition.

When we send or receive the bytes in i2c, we always get a NACK bit or ACK bit after each byte of the data is transferred during the communication.

In I2C, one bit is always transmitted on every clock. A byte which is transmitted in I2C could be an address of the device, the address of register or data which is written to or read from the slave.

In I2C, SDA line is always stable during the high clock phase except for the start condition, stop condition and repeated start condition. The SDA line only changes their state during low clock phase.

Note: SDA can only change their state only SCL is low except the start, repeated start and stop condition.

Handshaking Process in I2C Protocol

In I2C for each byte, an acknowledgment needs to be sent by the receiver, this acknowledgment bit is a proof that data is properly received by the receiver and it wants to continue the communication.

A master starts the communication to assert a start condition on the bus. After the start condition master is transmitted a 7-bit address with associated a read or write bits ( here I am discussing 7-bit address).

After the transmission of the address byte, master release the data lines to put the data line (SDA) in high impedance state, which allows the receiver to give the acknowledgment.

If this transmitted address is matched with any receiver then it pulls down the SDA lines low for the acknowledgment and after the acknowledgment, it releases the data lines. The master generates a clock pulse to read this acknowledgment bit and continue the read or write operation.

If this transmitted address is not matched with any receiver then nobody is pull down the data lines low, master understands it is a NACK and in that situation, master asserts a stop bit or repeated start bit for further communication.

Acknowledge (ACK) and Not Acknowledge (NACK)

In above lines, I have already described the ACK (acknowledgment) and NACK (Not Acknowledgement) bits and their importance in I2C protocol.

In below section, I am describing some scenario, where NACK bit is generated.

When the receiver is unable to receive or transmit the data, in that situation it generates a NACK bit to stop the communication.
During the communication, if the receiver gets any data or commands which are not understood by the receiver then it generates a NACK bit.
During the transfer, if the receiver performs any real-time operation and not able to communicate with master then assert a NACK bit.
When Master is a receiver and reads the data from the slave, then after the reading of whole data it asserts a NACK bit on data lines to stop the communication.
If there is no device present in the I2c bus of the same address which is transmitted by the master, then the master will not get the acknowledge by any slave and treat this situation as NACK.

I2C write operation

In I2c before the performing, the write operation master has to assert a start condition on I2c bus with the slave’s address and write control bit (for write operation control bit will be 0).

If the transmitted address match with any slave which connected to the I2C bus then master receives an acknowledge bit. After getting the ACK bit master send the address of the register, where it wishes to write, the slave will acknowledge again, letting the master know it is ready for the write operation.

After getting this acknowledgment, the master will start sending the data to the slave. Master will get the acknowledgment of each transmitted byte of data.

If the master does not get the acknowledgment from the slave then master assert a stop condition to stop the communication or either assert the repeated start to establish a new communication. There or another option to stop the communication when the master has sent all the data than the master is terminated the transmission with a STOP condition.

I2C Read operation

I2c Read operation same as the I2C write operation, In which master asserts the start condition before the read operation. After the start condition master transmit the slave address with Read control bit (for read operation control bit will be 1), if the transmitted address match with any device in the I2c bus then it acknowledges to the master to pulling down the data bus(SDA).

After getting ACK bit, master release the data bus but continue sending the clock pulse, in that situation master become receiver and slave become the slave transmitter.

In the read operation, the master gives the acknowledgment to the slave on the receiving of every byte of data to let the slave know that it is ready for more data. Once the master has received the number of bytes which it is expecting, it will send a NACK bit to release the bus and assert the stop bit to halt the communication.

Some Special cases in I2C

Clock synchronization in I2C

Unlike Rs232, I2c is synchronous communication, in which clock is always generated by the master and this clock is shared by both master and slave.
In the case of multi-master, all master generate their own SCL clock, hence it is necessary that clock of all master should be synchronized. In the i2C, this clock synchronization is done by wired and logic.

For the better understanding, I am taking an example, where two masters try to communicate with a slave. In that situation, both masters generate their own clock, master M1 generate clk1 and master M2 generate clk2 and clock which observed on the bus is SCL.

The SCL clock would be the Ending (clk1 & clk2) of clk1 and clk2 and most interesting thing is that highest logic 1 of SCL line defines by the CLK which has lowest logic 1.

Arbitration in I2C

The arbitration is required in case of multi-master, where more than one master is tried to communicate with a slave simultaneously. In I2C arbitration is achieved by the SDA line.

For Example,
Suppose two masters in the I2C bus is tried to communicate with a slave simultaneously then they will assert a start condition on the bus. The SCL clock of the I2c bus would be already synchronized by the wired and logic.

In the above case, everything will be good till the state of SDA line will same what is the masters driving on the bus. If any master sees that the state of SDA line differs, what is it driving then they will exit from the communication and lose their arbitration.

Note: Master which is losing their arbitration will wait till bus become free.

Clock stretching in I2C

In I2c, communication can be paused by the clock stretching to holding the SCL line low and it cannot continue until the SCL line released high again.

In I2C, slave able to receive a byte of data on the fast rate but sometimes slave takes more time in processing the received bytes in that situation slave pull the SCL line to pause the transaction and after the processing of the received bytes, it again released the SCL line high again to resume the communication.

The clock stretching is the way in which slave drive the SCL line but it is the fact, most of the slave do not drive the SCL line

Note: In I2c communication protocol, most of the I2C slave devices do not use the clock stretching feature, but every master should support the clock stretching.

Advantages of I2C communication protocol

There is a lot of advantage of I2C protocol which makes the user helpless to use the I2C protocol in many applications.

It is the synchronous communication protocol, so no need of precise oscillators for the master and slave.
It requires only two wire, one wire for the data (SDA) and other wire for the clock (SCL).
It provides the flexibility to the user to select the transmission rate as per the requirements.
In I2C Bus, each device on the bus is independently addressable.
It follows the master and slave relationships.
It has the capability to handle the multiple masters and multiple slaves on the I2C Bus.
I2C has some important features like arbitration, clock synchronization, and clock stretching.
I2C provide ACK/NACK (acknowledgment/ Not-acknowledgement) features which provide the help in error handling.

Some important limitation of I2C communication protocol

An I2C protocol has a lot of advantage but beside it, I2C has a few limitations.

It consumes more power than other serial communication busses due to open-drain topology.
It is good only for the short distance.
I2C protocol has some limitation for the number of slaves, the number of the slave depends on the capacitance of the I2C bus.
It only provides few limited communication speed like 100 kbit/s,400 kbit/s etc.
In I2c, devices can set their communication speed, slower operational devices can delay the operation of faster speed devices.

Conclusion

An I2c is the easy and cheap communication protocol; It can be multi-master or multi-slave. In I2c we get the acknowledgment (ACK) and not acknowledgment (NACK) bits after the each transmitted byte. Some disadvantage also attaches with I2C, it is a half-duplex communication and slow as compared to SPI (serial peripheral communication).

I2C EEPROM Basics and Bus Addressing Tutorial

These i2c memories come in many variants, like:

24C01 - 1Kbits (128 bytes)
24C02 - 2Kbits (256 bytes)
24C04 - 4Kbits (512 bytes)
24C08 - 8Kbits (1KB)
24C16 - 16Kbits (2KB)
24C32 - 32Kbits (4KB)
24C64 - 64Kbits (8KB)
24C128 - 128Kbits (16KB)
24C256 - 256Kbits (32KB)
24C512 - 512Kbits (64KB)
24C1024 - 1Mbits (128KB)

The memories behave as slave devices in the i2c protocol with all memory operations synchronized by the serial clock. The I2C EEPROM carry a built-in 4-bit unique identification code (0b1010) corresponding to the I²C Bus definition followed by 3 bits of device or block select bits.

Most of the EEPROMs have 3 configurable address bits some have only two e.g. with 256 or 512Kbit EEPROMs. This lets you to cascade multiple I2C EEPROMs on same I2C Bus. As you can see in the figure above A0, A1 and A2 are the address select bits. The final address of EEPROM always depends on configuration of address select pins.

7-Bit EEPROM Address: 1010 A2 A1 A0

Lets say If you connect A0, A1 and A2 to GND in your circuit then, addresses will be as follows:

7-Bit EEPROM Address: 1010000 = 0x50

I2C address for Write: 10100000 = 0xA0

I2C address for Read: 10100001 = 0xA1

AT24C1024 (1MBit EEPROM Addressing)

For 24C1024 (1Mbit EEPROM) addresses are little different. There is an internal block select bit to select between upper and lower 64KB of EEPROM memory as shown below.

So with block select use can select to read/write the upper and lower 64KB area of EEPROM memory, So Single 1Mbit eeprom has two internal addresses of its own.

Lower 64KB address (A0, A1 to GND):

7-Bit Address: 1010 0 00 = 0x50

I2C address for Write: 1010 0 00 0 = 0xA0

I2C address for Read: 1010 0 00 1 = 0xA1

Upper 64KB address (A0, A1 to GND):

7-Bit Address: 1010 1 00 = 0x54

I2C address for Write: 1010 1 00 0 = 0xA8

I2C address for Read: 1010 1 00 1 = 0xA9

Internal Sub-Address for EEPROMs

The sub address (also called word address) is used to point to the internal address of EEPROM. After sending slave address of the EEPROM master must send the sub-address to set the internal address pointer to memory location where read/write should take place. Once the address pointer is set, it auto interment for every sequential read/write operation. However in-case of write operation sub address is bound to page boundary limits. For EEPROM with less than 256bytes of memory area sub address size is 1 byte, whereas for others its 2 bytes.

So I2C transaction looks like this:

[Start] [Slave Address | R/W] [A] [Sub Address] [A] [Data] [A] ... [Data] [NAK] [Stop]

Write Operations

There are two types of write operations possible on I2C EEPROMs

1. Byte Write

2. Page Write

As soon as a I2C write finishes EEPROM enters into an internal self timed write cycle to finish the write operation on a memory location. This time is typically not more than 5ms. All inputs are disabled during this write cycle and EEPROM will not respond to any I2C operation until write cycle is finished.

Byte Write

This mode is a very similar to normal I2C write operation with only 1 byte of data written to EEPROM at a time. Following the start condition master sends the slave address and sub address after receiving acknowledge from slave (memory). The sub address sets the internal address pointer to memory location on EEPROM. Master device will then sends the data to be written to addressed memory location followed by a stop condition on by Master.

Page Write

A Page write is initiated the same was as byte write operation but master device does not send stop condition after the first data byte, Instead after the first data is acknowledged by EEPROM master can send data continuously upto the page boundary. e.g. if EEPROM has page size of 64 bytes then master device can send 64 bytes before sending a stop condition. This increases the write efficiency of EEPROM as the write cycle take same amount of time for both byte and page write.

To know about the page size of any I2C EEPROM memory, download datasheet of that EEPROM and look into first page under "Features".

Acknowledgement Polling

As explained in the Write operation section, the EEPROM will not acknowledge during a write cycle. This can be used to determine when the write cycle is completed. This will help increase the bus throughput. So instead of giving delay, you can poll EEPROM to know when it is ready to accept further commands.

Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. polling can be initiated immediately. This involves the master sending a Start condition, followed by the slave address with R/W bit as 0. If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and slave address must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. This is explained by a simple flow chart here:

Programming For EEPROM

Follow example is based on the I2C Implementation on 8051, so subroutine calls will have same name as mentioned in that tutorial. I am assuming that AT24C512 (512Kbit) eeprom is connected to 8051 microcontroller.

Assembly Sample

Following Assembly code example shows all the EEPROM operations:

;*****************************************

; I2C EEPROM (AT24C512) Byte Write

;*****************************************

Acall startc ;Call start condition

mov a, #0A0H ;Slave address

Acall send ;Send slave Address to I2C bus line

; 2-Byte Sub Address

Mov a, #00H ;Memory Location to be read/write

Acall send ;Send slave Address to I2C bus line

Mov a, #00H ;Memory Location to be read/write

Acall send ;Send slave Address to I2C bus line

Mov a, #55H ;Send Data 55H

Acall send ;Send slave Address to I2C bus line

Acall stop ;Call stop condition

;*****************************************

; I2C EEPROM (AT24C512) 64-Byte Page Write

;*****************************************

acall startc ;Call start condition

mov a,#0A0H ;Slave address

acall send ;Send slave Address to I2C bus line

; 2-Byte Sub Address

Mov a, #00H ;Memory Location to be read/write

Acall send ;Send slave Address to I2C bus line

Mov a, #00H ;Memory Location to be read/write

Acall send ;Send slave Address to I2C bus line

Mov r0, #64 ; Move the Data to be send to R0, indirect addressing mode

Again:

Mov a, r0 ; Move R0 to Acc. indirect addressing mode

Acall send ;Send slave Address to I2C bus line

DJNZ r0, again ;Decreament the content of r0 by 1 and check for 0

Acall stop ;Call stop condition

;*****************************************

; I2C EEPROM (AT24C512) Read Data

;*****************************************

Acall startc ; Call start condition

Mov a, #0A0H ; Slave address

Acall send

;2-Byte Sub Address

Mov a, #00H ;Memory Location to be read/write

Acall send ;Send slave Address to I2C bus line

Mov a, #00H ;Memory Location to be read/write

Acall send ;Send slave Address to I2C bus line

acall rstart ;Call restart condition

;Slave address writh Read bit

mov a,#0A1H ;Slave address with read bit

acall send ;Send slave Address to I2C bus line

mov r0, #9 ;Read 10 Bytes

mov r1, #50H ;Load read location (50H) in R1

Read more:

Acall read ;Call read function

Acall ack ;Call Ack function

Mov @r1, a ;Read a byte of Data from the slave

Inc r1 ;Increment the content of r1 by 1

Djnz r0, read more ;Decrement the content of r0 by and check foe 0

Acall read ;Call read function

Acall nak ;Call Nak function

Mov @r1, a ;Move the remaining 1 byte to r1

Acall stop ;Call stop condition

;*****************************************

; I2C EEPROM (AT24C512) ACK Polling

;*****************************************

eeprom_not_ready:

acall startc ;Call start condition

mov a,#0A0H ;Slave address

acall send ;Send slave Address to I2C bus line

acall stop ;Call stop condition

jc eeprom_not_ready ;When carry (ACK bit) is 0 it means EEPROM Has acknowledged and its ready for next operation

CasinoDigitalTech